Douglas Reeves


Old Papers


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Most of my research papers for the last 10 years are listed under the corresponding research project web pages. Recent papers may also be found here. Below are just papers that don't otherwise have a home, and are not recent.

  • W. Alexander, D. Reeves, and C. Gloster , ``Parallel Image Processing with the Block Data Parallel Architecture'', IBM Journal of Research and Development , Vol 4, No 5, September 2000.
  • W. Alexander, D. Reeves, and C. Gloster , ` `Parallel Image Processing with the Block Data Parallel Architecture'', Proceedings of the IEEE , Vol. 84, No. 7, July 1996, pp. 947--968.
  • S. Rampal , and D. Reeves. ``Routing and Admission Control Algorithms for Multimedia Traffic'' , Computer Communications , North-Holland Publ . Co., Vol. 18, No. 10, October 1995, pp. 755-768.
  • S. Reeves and E. F. Gehringer , ``Adaptive Routing for Hypercube Multiprocessors: A Performance Study'' , Intl . Journal of High-Speed Computing , Vol. 6, Number 1 (January 1994), pp. 1-29.
  • M. Melton, T. Phan , D. Reeves, and D. VandenBout , ``VLSI Implementation of the TInMANN Neuron'' , IEEE Transactions on Neural Networks 3(3), May 1992, pp. 375:384.
  • S. Reeves and M. J. Irwin, ``Fast Methods for Switch-Level Verification of MOS Circuits'', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6(5), September 1987, pp. 766:779.
  • H. Wang, K. Shin, H. Xin , and D. Reeves, ``A Simple Refinement of Slow-start of TCP Congestion Control'', Intl. Symp . on Computing and Communications (ISCC 2000) , July 2000.
  • G. Cato and D. Reeves, ``Parallel Task Scheduling with the Order Graph Method'' , IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, May 1996.
  • H. Salama , D. Reeves, Y. Viniotis , and T. Sheu . ``Evaluation of Multicast Routing Algorithms For Distributed Real-Time Applications in High-Speed Networks'' , 6th IFIP Conf. on High-Speed Networks, Chapman-Hall Publ ., September 1995.
  • S. Rampal , D. Reeves, and D. Agrawal . ``End-to-End Guaranteed QoS with Statistical Multiplexing for ATM Networks'', in Performance Modelling and Evaluation of ATM Networks , ed. D. Kouvatsos , Chapman and Hall Publ ., 1995.
  • G. Cato, and D. Reeves. ``Parallel Task Scheduling using the Order Graph Method'', in Proc . of the Phoenix Conf. on Computers and Communication , IEEE, Phoenix AZ , April 1995.
  • S. Alexandre , W. Alexander, D. Reeves, ``A Programmable Simulator for Analyzing the Block Data Flow Architecture'', Proc. of the 2nd Intl. Workshop on Modelling , Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS'94), IEEE Computer Society Press, 1994.
  • S. Howard, W. Alexander, D. Reeves, ``Simulation and Performance Evaluation of a Parallel Architecture for Signal Processing'', Proc. of the 26th Southeastern Symposium on System Theory, IEEE Computer Society, March 1993.
  • C. Aras , R. Luo , and D. Reeves, `` The Segmented Bus: A Dynamically Segmentable Interprocessor Communication Network for Intelligent Robot Systems'', Proc. of Intl. Conf. on Intelligent Robots and Systems , July 1992, IEEE.
  • D. Reeves, ``Group Address Recognition with Perfect Hashing Hardware'' , Proc . of IEEE Workshop on Architecture and Implementation of High-Performance Communication Subsystems , February 1992.
  • C. Aras , R. Luo , and D. Reeves, ``Improving Hierarchical Architecture Performance with Dynamic Segmentation'', Proc. of Intl. Conf. on Systems, Man, and Cybernetics , Volume II, October 1991, IEEE Computer Society, pp. 801:806.
  • M. Siegle , D. Reeves, and K. Kozminski , ``The Interlocking Bus Network for Fault-Tolerant Processor Arrays'' , Proc . of the 5th Intl. Conf. on Fault-Tolerant Computing Systems , Sept. 1991.
  • S. Rajgopal , K. Hedlund , and D. Reeves, ``Integrating Hardware Verification with CHDLs '' , Proc . of Tenth Intl. Symp . on Computer Hardware Description Languages , April 1991, North-Holland, pp. 133:144.
  • S. Rajgopal , K. Hedlund , and D. Reeves, ``Integrating Hardware Verification with Computer-Aided Design Systems'' , Proc . of the Workshop on Formal Methods in VLSI Design , January 1991, North-Holland.
  • M. Melton, T. Phan , D. Reeves, and D. Vandenbout , ``VLSI Implementation of the TInMANN Architecture'', Proc. of the IEEE Conf. on Neural and Information Processing Systems. Published as Advances in Neural Information Processing Systems 3, ed. by R. Lippmann , J. Moody, and D. Touretzky , Morgan-Kaufmann, 1991.
  • F. Brglez , G. Kedem , K. Kozminski , and D. Reeves, ``Rapid Prototyping of Digital ICs: Programming the Silicon'' , Proc . of the Canadian Conf. on VLSI , Oct. 1990.
  • D. Reeves, E. Gehringer , and A. Chandiramani , ``Adaptive Routing and Deadlock Recovery: A Simulation Study'' , Proc . of the 4th Conf. on Hypercubes and Concurrent Computers , March 1989, pp. 331:338.
  • D. Reeves and M. Irwin, ``Functional Verification of Digital MOS Circuits'' , Proc . of Intl. Conf. on Computer-Aided Design, Nov. 1986, IEEE Computer Society, pp. 496:499.

 


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